Time-to-market of new, innovative product designs is critical in the fast-moving, competitive semiconductor industry. But
with suppliers’ brand reputations at stake, extensive testing must be performed during the device development phase to ensure
the long-term reliability of every aspect of their products, which need to function consistently in a vast array of challenging
customer environments.
Reliability validation can be a lengthy process based on Highly Accelerated Stress Testing, whereby the semiconductor device
under test (DUT) is cycled through environmental extremes of temperature, humidity, and mechanical stress. The goal is
to cause the device to fail—the failure mechanism can then be investigated—and any potential problems rectified.
During or following each applied stress cycle, the DUT typically undergoes some form of parametric testing, which involves
the electrical testing and characterization of dedicated test structures manufactured on the semiconductor wafer or package
substrate to verify whether the specific structures still satisfy the required design criteria. These tests are typically
performed by a Source/Measurement Unit (SMU) and range from simple resistance measurements to scanned current versus
voltage (IV) or capacitance versus voltage (CV) measurements, usually made via Kelvin 4-wire connections to eliminate
instrument-to-DUT interconnection resistance, as illustrated in Fig.1
Fig.1 Kelvin 4-terminal resistance measurement configuration
With the total number of DUT pins potentially running into hundreds or even thousands when testing, for example, the latest
server CPU packages, a high pin-count automated switching system is required to quickly and reliably connect the SMU sequentially
across pairs of DUT pins for each parametric test, —with two individual test connections needed on every pin for the 4-wire
measurements.
With IC designers constantly striving to accelerate reliability testing without compromising quality, a parametric test system
must be designed to minimize the test time for this large number of DUT pins. One relatively straightforward way
of achieving this goal is to connect two SMUs in parallel to different pairs of DUT pins and record their parametric
measurements simultaneously, effectively halving the overall test time. Building upon this strategy, Pickering has worked
closely with leading semiconductor manufacturers to produce a high pin-count switch matrix platform specifically optimized
for very fast, 4-wire parametric testing by simultaneously connecting up to 12 SMUs to the DUT in parallel.